The present invention generally relates to an Integrated Circuit (IC), and more specifically, to a system and method for testing memory blocks in a System on Chip (SOC).
Recently, individual electronic circuits are being integrated onto a single chip, as opposed to having a variety of IC chips being assembled on a circuit board to form a system. These electronic circuits may include functional logic blocks and arrays of memory blocks. In the SOC, the testing and debugging of the functional logic blocks and the arrays of the memory blocks is a matter of major concern.
Currently, boundary-scan testing is a widely used method for testing sub-blocks in an SOC design, since it can be performed without the use of physical test probes. Boundary-scan testing of SOC designs involves boundary-scan signals, known as Test Access Ports (TAPs) signals, being applied through a fixed number of test pins on the SOC. With the acceptance of standard scan-based TAPs such as the IEEE-1149.1-1990 standard, testing SOC designs and in-chip diagnostics has become comparatively easy. A built-in self-test (BIST) is a mechanism used to automatically verify a complete SOC design or a portion of an SOC design. BIST enables automatic generation of test patterns for testing a design, as compared to manual test vector generation. A memory built-in self-test (MBIST) architecture is used to test memory blocks in an SOC design. This circumvents the problem of generating test vectors for testing memory blocks, since the procedure of generating a set of vectors for a large die area of memory in an SOC chip is complex.
Testing of the memory arrays in an SOC design often requires the help of external vendors. Electronic Design Automation (EDA) MBIST tools provided by an external vendor can be used to thoroughly test large memory arrays. However, the major disadvantage of an EDA MBIST tool is that it cannot read the TAP of the SOC design. EDA MBIST tools generate their own TAP (hereinafter referred to as an EDA tool TAP) and provide instructions and test data during the process of testing of the memory arrays. For security reasons, a typical SOC does not allow the TAPs to be combined with the EDA tool TAP. Some external vendors provide a top-level selection pin for making a selection between the SOC TAP and the EDA tool TAP. However, this results in a design that is not secure. For example, in such a design flow, it could be possible for a user to access information stored in a memory array via the EDA tool TAP.